DS1372U+T&R【PDF 6/12 页】IC BINARY COUNTER 32-BIT 8-USOP

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DS1372

_______________________________________________________________________________________

Note 1:

Limits at -40°C are guaranteed by design and not production tested.

Note 2:

All voltages are referenced to ground.

Note 3:

SCL clocking at maximum frequency = 400kHz.

Note 4:

Specified with I2C bus inactive, SCL = SDA = VCC.

Note 5:

Measured with a 32.768kHz crystal attached to the X1 and X2 pins.

Note 6:

The I2C minimum operating frequency is imposed by the requirement of timeout period.

Note 7:

The first clock pulse is generated after this period.

Note 8:

A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIHMIN of the SCL sig-

nal) to bridge the undefined region of the falling edge of SCL.

Note 9:

The maximum tHD:DAT must only be met if the device does not stretch the low period (tLOW) of the SCL signal.

Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT

≥ 250ns must then be met.

This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch

the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns

before the SCL line is released.

Note 11: CB = Total capacitance of one bus line in pF.

Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of

2.4V

≤ VCC ≤ VCC(MAX).

Note 13: The DS1372 can detect any single SCL clock held low longer than T_TIMEOUT (MIN). The I2C interface is in reset state and

can receive a new START condition when SCL is held low for at least T_TIMEOUT (MAX). Once the part detects this condi-

tion the SDA output is released. The oscillator must be running for this function to work.

ELECTRICAL CHARACTERISTICS (continued)

(VCC = 2.4V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Fast mode

100

Data Setup Time (Note 10)

tSU:DAT

Standard mode

250

Fast mode

20 +

0.1CB

300

Rise Time of SDA and SCL

Signals (Note 11)

Standard mode

20 +

0.1CB

1000

Fast mode

20 +

0.1CB

300

Fall Time of SDA and SCL Signals

(Note 11)

Standard mode

20 +

0.1CB

300

Fast mode

0.6

Setup Time for STOP Condition

tSU:STO

Standard mode

4.0

μs

Capacitive Load for Each Bus

Line (Note 11)

400

I/O Capacitance

CI/O

SCL Spike Suppresion

TSP

Oscillator Stop Flag (OSF) Delay

(Note 12)

tOSF

100

Timeout Interval (Note 13)

T_TIMEOUT

CRYSTAL SPECIFICATIONS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Nominal Frequency

32.768

kHz

Capacitive Load

12.5

Equivalent Series Resistance

ESR

I2C, 32-Bit, Binary Counter Clock with 64-Bit ID

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